Receiving Apparatus, Receiving System Using Same, And Receiving Method Thereof

ABSTRACT

A receiving apparatus ( 100 ) includes demodulation parts ( 101, 102 ) for receiving the respective one of received signals of broadast systems to output demodulated data and timing clocks synchronized with the respective demodulated data, a clock generating part ( 103 ) for outputting, to an A/V decoder ( 107 ), the two timing clocks from the demodulation parts ( 101, 102 ) as high-rate and low-rate timing clocks and for outputting a control signal for multiplexing the two demodulated data from the demodulation parts ( 101, 102 ), and a multiplexing part ( 104 ) for multiplexing, based on the control signal, the two demodulated data to output the multiplexed data to the A/V decoder ( 107 ). The A/V decoder ( 107 ) receives the multiplexed data and timing clocks from the receiving apparatus ( 100 ) to process the video/audio signals of each broadcast.

TECHNICAL FIELD

The present invention relates to a receiving apparatus for receiving a plurality of digital broadcastings of different broadcast systems or same broadcast systems such as a satellite digital broadcasting or a ground digital broadcasting, and a receiving system using this receiving apparatus and a receiving method thereof.

BACKGROUND ART

Recently, the digitalization of a broadcast and a communication has been progressed with the advancement of a digital transmission technology and a semiconductor integrated technology.

A receiving apparatus and a receiving system which simultaneously receive a plurality of broadcastings are constituted by a plurality of demodulation parts for demodulating a received signal in response to each broadcast system, a multiplexing part for multiplexing demodulated data outputted by respective demodulation parts, a multiplexed separating part for separating the demodulated data decoded from the demodulated data to be multiplexed thereby, and a decoding part for decoding the demodulated data separated by the multiplexed separating part.

An example of such a digital broadcasting apparatus is shown in JP-A-11-122556.

This well-known digital broadcasting receiver includes a demodulation part tuned to each broadcast system, a multiplexing part for receiving the demodulated data by the transport packet and multiplexing the demodulated data by the transport packet at a rate over a total of transport packet transmission rates of the respective broadcast systems, and a multiplexed separating part for separating decoded and demodulated data from the multiplexed demodulated data, so as to simultaneously receiving a plurality of broadcast systems.

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention

However, in a well-known digital broadcasting receiving apparatus, there was a problem that since a large-sized memory circuit such as a memory for delaying respective demodulated data was required and a size of the memory circuit was increased to multiplex the demodulated data outputted from a plurality of multiplexing parts in response to respective broadcast system at a rate over a total of transport packet transmission rates of the respective broadcast systems by the transport packet, a well-known digital broadcasting receiving apparatus, the well-known digital broadcasting receiving apparatus was expensive. In addition, in the well-known digital broadcasting receiving apparatus, a system for multiplexing the demodulated data was not specifically disclosed.

Consequently, an object of the present invention is to provide an inexpensive receiving apparatus capable of multiplexing two demodulated data adding a small-sized circuit without using a large-sized memory, a receiving system using this receiving apparatus, and a receiving method thereof.

Means to Solve the Problem

In order to achieve the object, the present invention is characterized in that the receiving apparatus includes two demodulation parts that respectively input received signals of respective broadcast systems, and output demodulated data thereof and timing clocks respectively synchronized therewith; a clock generating part that outputs the two timing clocks outputted from the demodulation parts, as a high-rate timing clock and a low-rate timing clock to an A/V decoder, and outputs control signals for multiplexing the two demodulated data outputted from the demodulation parts; and a multiplexing part that multiplexes the two demodulated data and outputs them to the A/V decoder, based on the control signals. The A/V decoder processes audio/video signals of respective broadcastings by using the demodulated data and the timing clocks outputted from the receiving apparatus as the inputs.

ADVANTAGE OF THE INVENTION

By the configuration, two demodulated data can be multiplexed by adding a small-scale circuit without using a large-scale memory, the reduction in costs and power consumption can be realized by reducing a circuit scale, timing clocks synchronized with the demodulated data to be multiplexed can be synchronized with single timing clock including higher-rate internal timing clock, and a timing restriction of latter A/V decoder (video signal processing device) can be relaxed. Accordingly, the present invention has an advantage of constructing a more inexpensive system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a receiving apparatus in embodiment 1 of the present invention.

FIG. 2 is a block diagram of a clock generating part of the receiving apparatus.

FIG. 3 is a block diagram of a rate determination part of the receiving apparatus.

FIG. 4 is a timing diagram showing an operation of the receiving apparatus.

FIG. 5 is a block diagram of a receiving apparatus in embodiment 2 of the present invention.

FIG. 6 is a block diagram of a clock generating part of the receiving apparatus.

FIG. 7 is a block diagram of a multiplexing part of the receiving apparatus.

FIG. 8 is a timing diagram showing an operation of the receiving apparatus.

FIG. 9 is a block diagram of a receiving apparatus in embodiment 3 of the present invention.

FIG. 10 is a timing diagram showing an operation of the receiving apparatus.

FIG. 11 is a block diagram of a receiving apparatus in embodiment 4 of the present invention.

FIG. 12 is a block diagram of a receiving apparatus in embodiment 5 of the present invention.

FIG. 13 is a flow chart of a receiving method of the receiving apparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1

FIG. 1 is a block diagram of a receiving apparatus in embodiment 1 of the present invention.

In FIG. 1, reference numeral 100 indicates a receiving apparatus. The receiving apparatus 100 receives two received signals A and B of digital broadcasting of different broadcast systems or same broadcast systems, and outputs multiplexed data to multiplex the outputs of respective demodulated data, and high-rate timing clocks and low-rate timing clocks synchronized with the multiplexed data. In addition, reference numeral 107 indicates an A/V decoder (an example of a video signal processing device). The A/V decoder 107 separates the multiplexed data into two demodulated data for decoding, and uses any one or both of the two demodulated data so as to process an audio/video signal of each broadcasting by using the multiplexed data, high-rate timing clocks and low-rate timing clocks outputted from the receiving apparatus 100 as the inputs.

The receiving apparatus 100 includes a first demodulation part 101 and a second demodulation part 102, a rate determination part 105, a first selection part 106, a clock generating part 103, and a multiplexing part 104.

The first and second demodulation parts 101 and 102 respectively input the two received signals A and B, and output demodulated data D1 and D2 to the first selection part 106, and timing clocks T1 and T2 respectively synchronized therewith to the selection part 106 and the rate determination part 105.

The rate determination part 105 compares the respective rates of the two timing clocks T1 and T2 outputted from the first and second demodulation parts 101 and 102, determines which clock is the higher-rate, and outputs the determination result to the first selection part 106 as a control signal C3 by using the two timing clocks T1 and T2 respectively outputted from the demodulation parts 101 and 102 as the inputs.

The first selection part 106 selects any one of the timing clocks T1 and T2 outputted from the first and second demodulation parts 101 and 102 as a high-rate timing clock TH to output it to the clock generating part 103, and outputs the other one to the clock generating part 103 as the timing clock TL, and selects any one of the demodulated data D1 and D2 outputted from the first and second demodulation parts 101 and 102 as the high-rate demodulation data DH to output it to the multiplexing part 104, and outputs the other one to the multiplexing part 104 as the low-rate demodulated data DL as the low-rate demodulated data DL, based on a control signal C3 (determination result) outputted from the rate determination part 105.

The clock generating part 103 generates timing clocks of the demodulated data DH and DL to be multiplexed, that is, the high-rate timing clock of the high-rate demodulated data DH and the low-rate timing clock of the low-rate demodulated data DL to output them to the A/V decoder 107, and outputs control signals for multiplexing the two demodulated data DH and DL to the multiplexing part 104 by using the high-rate timing clock TH and the low-rate timing clock TL outputted from the first selection part 106 (based on the two timing clocks outputted from the demodulation parts 101 and 102) as the inputs.

The multiplexing part 104 multiplexes the demodulated data DH and DL outputted from the first selection part 106 by a byte, based on the control signals outputted from the clock generating part 103, and outputs the demodulated data to the A/V decoder 107.

Moreover, the first and second demodulation parts 101 and 102 are the demodulation parts suitable for the broadcasting systems of the respective received signals A and B.

FIG. 2 shows a circuit configuration more specific than that of the clock generating part 103.

The clock generating 103 outputs the high-rate timing clock TH to the A/V decoder 107 as the high-rate timing clock as shown in FIG. 2 by using the high-rate timing clock TH and the low-rate timing clock TL outputted from the first selection part 106 as the inputs.

In addition, the clock generating part 103 includes a delaying unit 201, an edge detecting unit 202, a second selection unit 203 and a control signal generating unit 204, as shown in FIG. 2.

The delaying unit 201 inputs the low-rate timing clock TL for delaying and outputs the timing clock TLD to the second selection unit 203.

The edge detecting unit 202 detects simultaneous rises of the timing clocks, and outputs a logical value “1” (an example of a second logical value) when the rises are simultaneous and a logical value “0” (an example of an inverting value of the second logical value) when the rises are not simultaneous, to the second selection unit 203 as a selection signal SL by using the high-rate timing clock TH and the low-rate timing clock TL as the inputs.

The second selection unit 203 inputs the low-rate timing clock TL and the timing clock TLD outputted from the delaying unit 201, selects the two timing clocks based on the selection signal SL, that is, selects the timing clock TLD delayed when the selection signal SL has a logical value “1” and selects the low-rate timing clock TL when the selection signal SL has a logical value “0”, and outputs the low-rate timing clock TL to the control signal generating unit 204 and the A/V decoder 107 as the low-rate timing clock.

The control signal generating unit 204 inputs the low-rate timing clock and the high-rate timing clock TH outputted from the second selection unit 203, outputs a logical value “1” (an example of a third logical value) when the high-rate timing clock TH rises and a logical value “0” (an example of an inverting value of the third logical value) when the low-rate timing clock rises, and holds the values when a rise does not exist, to the multiplexing part 104 as the control signal identifying the demodulated data DH and DL selected in the multiplexing part 104.

In addition, FIG. 3 shows a circuit configuration more specific than that of the rate determination part 105.

The rate determination part 105 includes a first clock counting unit 301 and a second clock counting unit 302, and an identification unit 303, as shown in FIG. 3.

The first and second clock counting units 301 and 302 input the two timing clocks T1 and T2 respectively outputted from the first and second demodulation parts 101 and 102, count respective numbers N1 and N2 of rises (number of clocks) of the timing clocks T1 and T2, output the respective initialization signals to the identification unit 303 as the control signals C1 and C2 at a predetermined cycle n, so as to initialize the timing clocks by the outputting of any one of the control signals (initialization signals) C1 and C2.

The identification unit 303 identifies the rate determination result, and outputs “1” (an example of a first logical value) in case that the control signal C1 is inputted to the first selection part 106 in advance or simultaneously and “0” (an example of the inverting value of the first logical value) in case that the control signal C2 is inputted in advance, as the control signal (identification signal) C3 outputted to the first selection part 106 by using the control signals C1 and C2 respectively outputted from the first and second clock counting units 301 and 302 as the inputs.

Moreover, the counting values N1 and N2 of the first and second clock counting units 301 and 302, and the control signals (initialization signals) C1 and C2 are outputted as shown in FIG. 3.

Operations of the receiving apparatus configured as above will be described. FIG. 4 is a timing diagram of each part in the receiving apparatus 100 shown in FIG. 1.

The first demodulation part 101 performs a demodulation processing suitable for the broadcast system, and outputs the timing clock T1 and the demodulated data D1 (A[1], A[2], A[3], . . . ) synchronized therewith. In addition, the second demodulation part 102 performs the demodulation processing suitable for the broadcast system, and outputs the timing clock T2 and the demodulated data D2 (B[1], B[2], B[3], . . . ) synchronized therewith.

The clock counting units 301 and 302 of the rate determination part 105 counts the rises of the timing clocks T1 and T2, and the outputs N1 and N2 of the counting values increase as shown in FIG. 4. In addition, since the predetermined cycle has n, a logical value “1” is outputted as the control signals (initialization signals) C1 and C2 initializing the clock counting units 301 and 302 when N1 and N2 are the same as n (timing 1 and timing 2 in FIG. 4). Further, both of the clock counting units 301 and 302 are initialized at the time when the cycle n of any one of the clock counting units 301 and 302 is in n.

The identification unit 305 of the rate determination part 105 identifies a clock having a high-rate output out of the timing clocks T1 and T2 considering that which one of the clock counting units 301 and 302 reaches the predetermined cycle, that is, which one of control signals C1 and C2 in advance reaches a logical value “1” to outputs a control signal C3 representing the result. In the embodiment 1, “1” is outputted when the timing clock T1 as the control signal C3 is high-rate, that is, the control signal is in advance or simultaneously inputted, and “0” is inputted when the timing clock T2, that is, the control signal C2 is in advance inputted.

The first selection part 106 outputs the timing clocks T1 and T2 as the high-rate timing clock TH and the low-rate timing clock TL, respectively when the logical value of the control signal C3 is “1”, and outputs the demodulated data D1 and D2 as the high-rate demodulate data DH and the low-rate demodulated data DL, respectively, as shown in FIG. 4. In addition, the first selection part 106 operates conversely when the logical value of the control signal C3 is “0”.

The clock generating part 103 outputs the inputted high-rate timing clock TH to the A/V decoder 107 as the high-rate timing clock without change.

The delaying unit 201 of the clock generating part 103 delays the low-rate timing clock TL to output the timing clock TLD. The edge detecting unit 202 compares the timing clocks TH and TL, and outputs a logical value “1” when the rises are simultaneous and a logical value “0” when the rises are not simultaneous, as the selection signal SL. The second selection unit 203 selects the timing clock TLD delayed when the selection signal SL has the logical value “1” and the timing clock TL when the selection signal SL has the logical value “0”, so as to output the selected timing clocks to the A/V decoder as the low-rate timing clock.

The control signal generating unit 204 of the clock generating part 103 outputs a logical value “1” when the high-rate timing clock rises and a logical value “0” when the low-rate timing clock rises, as the control signal outputted to the multiplexing part 104 and holds the values when a rise does not exist.

The multiplexing part 104 selects the high-rate demodulated data DH when the control signal outputted from the control signal generating unit 204 has a logical value “1” and the low-rate demodulate data DL when the control signal outputted from the control signal generating unit 204 has a logical value “0”, and generates the multiplexed data from the demodulated data DH and DL as shown in FIG. 4, so as to output them to the A/V decoder 107.

As shown above, in embodiment 1, since the two demodulated data D1 and D2 can be multiplexed by adding small-scale circuits without using a storing unit (mass memory) for storing the two demodulated data D1 and D2 outputted by the two demodulation parts 101 and 102, the circuit scale and a cost can be reduced by miniaturizing the receiving apparatus 100. In addition, the number of output pins is reduced by the multiplex output so as to reduce the cost by the miniaturization of the receiving apparatus. Further, a deterioration of a jitter performance and an increment of a response time can be evaded so as to sequentially output the demodulated data without accumulating the demodulated data in the memory.

In addition, in embodiment 1, even when the rates of the demodulated data D1 and D2 are changed or when unknown (when the synchronized timing clocks T1 and T2 are changed or when unknown), the high-rate timing clock is determined by the rate determining clock 105, any one of the timing clocks T1 and T2 outputted from the demodulation parts 101 and 102 is selected and outputted as the high-rate timing clock TH by the first selection part 106, based on the determination result. Further, any one of the demodulated data D1 and D2 outputted from the first and second demodulation parts 101 and 102 is outputted as the high-rate demodulated data DH and the other one is outputted as the low-rate demodulated data DL. Therefore, the processing in one system including the multiplexing part 104 and the clock generating part 103 can be performed to reduce the circuit scale.

Further, in embodiment 1, it is possible to easily compare the timing clocks T1 and T2 with the small-scale circuit by using the clock counting units 301 and 302 as the rate determination part 105.

Besides, in embodiment 1, when the two timing clock T1 and T2 rise simultaneously, the timing clock TLD delayed by the delaying unit 201 is selected as the low-rate timing clock and the rise of the low-rate timing clock is delayed, so that the two demodulated data D1 and D2 can be multiplexed without being easily delayed and the reliability can be improved, by delaying a rise timing of the low-rate timing clock.

Moreover, varying the predetermined cycle n by the frequencies of the timing clocks T1 and T2 improves a performance of a jitter. For example, a generation part of the initialization signals (control signals C1 and C2) of the clock counting units 301 and 302 can be simplified and the circuit can be further miniaturized by multiplying the cycle n by 2.

In addition, when the rates of the timing clocks T1 and T2 are previously known, the rate determination part 105 and the first selection part 106 are excluded, so as to further miniaturize the circuit. Further, when the rates of the timing clocks T1 and T2 can be identified from outside, the only rate determination part 105 is excluded, so as to miniaturize the circuit.

Further, polarities or the logical values of the control signals indicated in embodiment 1 are determined as shown above.

Embodiment 2

Hereinafter, a receiving apparatus and a receiving method in embodiment 2 of the present invention will be described with reference to FIGS. 5 to 8 and FIG. 3. Same reference numerals are given to components same as those of embodiment 1 in FIGS. 1 and 3.

In embodiment 2, a clock generating part 501 is provided in place of the clock generating part 103 and a multiplexing part 503 is provided in place of the multiplexing part 104.

The clock generating part 501 of embodiment 2 inputs the counting values N1 and N2, the control signals (initialization signals) C1 and C2, and the control signal (identification signal) C3, inputs the high-rate timing clock TH from the first selection part 106, and outputs the high-rate timing clock TH as the high-rate timing clock, so as to generate and output a clock having a same average frequency as a low-rate timing clock TL and synchronized with the timing clock TH as the low-rate timing clock.

In addition, the multiplexing unit 503 of embodiment 2 inputs the high-rate demodulated data DH, the low-rate demodulated data DL and the low-rate timing clock TL from the first selection part 106, inputs the low-rate timing clock from the clock generating part 501, and selects the high-rate demodulated data DH and the low-rate demodulated data DL, based on the inputted low-rate timing clock, so as to generate the multiplexed data by a byte.

FIG. 6 shows a specific circuit configuration of the clock generating part 501.

The clock generating part 501 includes a third selection unit 601, a storing unit 602, a mask signal generating unit 603, a mask unit 604 and a logic inverting circuit 605.

The third selection unit 601 inputs the counting values N1 and N2, and the control signal C3 from the rate determination part 105, selects the counting value N1 of the first clock counting unit 301 when the control signal C3 has the logical value “1”, that is, the timing clock T1 is high-rate and the counting value N2 of the second clock counting unit 302 when the control signal C3 has the logical value “0”, that is, the timing clock T2 is high-rate, and outputs the selected counting values to the mask signal generating unit 603 as the counting value NH.

The storing unit 602 inputs the counting values N1 and N2, the control signals (initialization signals) C1 and C2, and the control signal C3, stores the counting value N2 outputted from the second clock counting unit 302 connected to the low-rate timing clock T2 as a control value M when the control signal C3 has the logical value “1” (when the timing clock T1 is high-rate) and the counting value N1 outputted from the first clock counting unit 301 connected to the low-rate timing clock T1 as the control value M when the control signal C3 has the logical value “0”, assuming that the control signals (initialization signals) C1 and C2 are inputted, and outputs the counting values to the mask signal generating unit 603.

The mask signal generating unit 603 inputs the counting value NH outputted from the third selection unit 601 and the control value M outputted from the storing unit 602, and outputs the logical value “1” (an example of the fourth logical value) to the mask unit 604 when the counting value NH of the third selection unit 601 as the mask signal is not larger than the control value M and the logical value “0” (an example of the inverting value of the fourth logical value) when the counting value NH of the third selection unit 604 is larger than the control value M to the mask unit 604.

The mask unit 604 inputs the high-rate timing clock TH outputted from the first selection part 106 and the mask signal outputted from the mask signal generating unit 603, and outputs the high-rate timing clock TH to the A/V decoder 107 and the multiplexing unit 503 as the low-rate timing clock when the mask signal has the logical value “1”, and the logical value “L” when the mask signal has the logical value “0”.

The logic inverting circuit 605 logic-inverts the high-rate timing clock TH outputted from the first selection part 106 and outputs the high-rate timing clock TH to the A/V decoder 107.

FIG. 7 shows a specific circuit configuration of the multiplexing part 503.

The multiplexing part 503 includes a FIFO unit 701 and a fourth selection unit 702 as shown in FIG. 7.

The FIFO unit 701 writes the low-rate demodulated data DL inputted from the first selection part 106 sequentially at the timings of the low-rate timing clock TL inputted from the first selection part 106, reads the low-rate demodulated data DL at the timings of the low-rate timing clock outputted from the clock generating part 501, and outputs the low-rate demodulated data DL to the fourth selection unit 702.

The fourth selection unit 702 selects the low-rate demodulated data DL outputted from the FIFO unit 701 when the low-rate timing clock outputted from the clock generating part 501 has the logical value “1” and the high-rate demodulated data DH when the low-rate timing clock has the logical value “0”, generates the multiplexed data, and outputs the multiplexed data to the A/V decoder 107.

FIG. 8 shows operations of the receiving apparatus configured as shown above.

The storing unit 602 stores the counting output N2 of the second clock counting unit 302 connected to the low-rate timing clock T2 as the control value M when the counting output N1 of the counting unit 301 at the timing 1 or 2 is in the predetermined cycle n. In FIG. 8, m is stored. In addition, the storing unit 602 is updated according to the control signal C1 (initialization timing) of the first clock counting unit 301.

The third selection unit 601 selects the counting value N1 of the first clock counting unit 301 connected to the high-rate timing clock T1 by the control signal C3 and outputs the counting value N1 as the counting value NH.

The mask signal generating unit 603 compares the counting value NH synchronized with and varied on the high-rate timing clock T1 outputted from the selection unit 601 with the control value M stored in the storing unit 602, and outputs the logical value “1” as the mask signal when the counting value NH is not larger than the control value M and the logical value “0” when the counting value NH is larger than the control value M.

The FIFO unit 701 writes the low-rate demodulated data DL at the timing of the low-rate timing clock TL and reads the low-rate demodulated data DL at the timing of the low-rate timing clock. The output of the FIFO unit 701 is synchronized with the low-rate timing clock and, at a burst, outputted as many as the control value M. The fourth selection unit 702 selects the output of the FIFO unit 701 when the low-rate timing clock has the logical value “1” and the high-rate demodulated data DH when the low-rate timing clock has the logical value “0”, and outputs the multiplexed data.

As described above, in embodiment 2, the two demodulated data DH and DL outputted by the two demodulation parts 101 and 102 are synchronized a timing clock synchronized with the high-rate timing clock, and the timings of the multiplexed outputs are equally spaced. A signal processing for processing the multiplexed outputs can be easily performed and an entire configuration of the receiving apparatus can be simplified. Furthermore, since a timing restriction of a latter A/V decoder 107 can be relaxed, a cheap A/V decoder can be used and the receiving apparatus can be inexpensively provided.

In addition, in embodiment 2, a low-rate timing clock having an average frequency same as the low-rate timing clock on the basis of the high-rate timing clock can be generated in the small-scale circuit.

Further, in embodiment 2, even though rates of the two demodulated data DH and DL outputted by the two demodulation parts 101 and 102, and the two timing clocks TH and TL synchronized therewith are unknown, the rate determination can be performed for selecting.

Moreover, in embodiment 2, even though the storing unit 602 requires the control value M by using the counting values N1 and N2, the control signals (initialization signals) C1 and C2, the control signal C3 required by the rte determination part 105, the clock generating part 501 includes a third clock counting unit which inputs the high-rate timing clock TH and the low-rate timing clock TL from the first selection part 106, and outputs the initialization signals at a cycle when the number of clocks of the high-rate timing clock TH is counted, being initialized, and a fourth clock counting unit which counts the number of clocks of the low-rate timing clock TL, being initialized, whereby the output of the fourth clock counting unit may be stored as the control value M by the initialization signals of the third clock counting unit. Then, the mask signal generating unit 603 inputs the control value M of the storing unit 602 and the counting value of the third clock counting unit, outputs “1” (a fourth logical value) as the mask signal when the counting value of the third clock counting unit is not larger than the control value M and “0” (an inverting value of the fourth logical value) as the mask signal when the counting value of the third clock counting unit is larger than the control value M. In addition, the clock generating part 501 inputs the high-rate timing clock TH and the low-rate timing clock TL from the selection part 106, generates a high-rate timing clock having the same average frequency as the low-rate timing clock TL, and outputs the high-rate timing clock and the low-rate timing clock.

Embodiment 3

Hereinafter, a receiving apparatus in embodiment 3 of the present invention will be described with reference to the drawings. Moreover, same reference numerals are given to components same as those of embodiment shown in FIG. 1 and the description thereof will be omitted.

FIG. 9 is a block diagram of the receiving apparatus in embodiment 3 of the present invention.

A receiving apparatus 100 includes demodulation parts 101 and 102, a first data extension part 901 and a second data extension part 902, a control signal generating part 903, a multiplexing part 904, a first clock generating part 905, and a second clock generating part 906.

The first and second data extension parts 901 and 902 input demodulated data D1 and D2, and timing clocks T1 and T2 respectively synchronized with the demodulated data D1 and D2, respectively outputs the timing clocks T1 and T2 alternatively, and split and output the timing clock T1 and T2 into T1 a, T1 b, T2 a and T2 b. Furthermore, the first and second data extension parts 901 and 902 latches the demodulated data D1 synchronized at the respective rises of the timing clocks T1 a and T1 b, generates the demodulated data D1 a and D1 b respectively synchronized with the timing clocks T1 a and T1 b, and latches the demodulated D2 at the respective rises of the timing clocks T2 a and T2 b and generates and outputs the demodulated data D2 a and D2 b respectively synchronized with the timing clocks T2 a and T2 b. That is, two systems including odd-time timing clocks and odd-time demodulated data synchronized therewith, and even-time timing clocks and even-time demodulated data are respectively outputted.

The control signal generating part 903 inputs a control timing clock Tp having a cycle T shorter than the shortest cycle of the timing clocks T1 and T2, and four demodulated timing clocks (timing clocks T1 a, T1 b, T2 a and T2 b) outputted from the first and second data extension parts 901 and 902, detects rises of the four demodulated timing clocks by using the control timing clock Tp, and outputs the data control signals (T1 a, T1 b, T2 a and T2 b; identification control signals) for identifying the timing clock detecting the rise at a next control timing clock cycle T(N+1) sequentially and when the rise is detected within the control timing clock cycle T(N), and holds and outputs the data control signal when the rise is not detected.

The multiplexing part 904 selects demodulated data D1 a, D1 b, D2 a and D2 b synchronized with the data control signals, which are outputted from the data extension parts 901 and 902, based on the data control signals (T1 a, T1 b, T2 a or T2 b) outputted from the control signal generating part 903, generates the multiplexed data, and outputs the multiplexed data to the A/V decoder 107.

The clock generating part 905 inputs the timing clock Tp, and the timing clocks T1 a and T1 b outputted from the first data extension part 901, detects the rises of the timing clocks T1 a and T1 b at the cycle of the control timing clock by using the control timing clock Tp, generates a first multiplexed timing clock Ta having the rise during the data control signal is outputted within the next cycle T[N+1] when any rise is detected within the control timing clock cycle T[N], and outputs the first multiplexed timing clock Ta to the A/V decoder 107.

The clock generating part 906 inputs the control timing clock Tp, and the timing clocks T2 a and T2 b outputted from the second data extension part 902, detects the rises of the timing clocks T2 a and T2 b at the cycle of the control timing clock by using the control timing clock Tp, generates a first multiplexed timing clock Tb having the rise during the data control signal is outputted within the next cycle T [N+1] when any rise is detected within the control timing clock cycle T[N], and outputs the second multiplexed timing clock Ta to the A/V decoder 107.

FIG. 10 shows operations of the receiving apparatus configured as described above.

The first data extension part 901 outputs the timing clock T1 alternatively by a cycle, and split and output the timing clock T1 into the timing clocks T1 a and T1 b. In addition, the first data extension part 901 latches the demodulated data D1 synchronized with the respective rises of the timing clocks T1 a and T1 b, and generates the demodulated data D1 a and D1 b respectively synchronized with the timing clocks T1 a and T1 b. Further, the second data extension part 902 outputs the timing clocks T2 a and T2 b, and the demodulated data D2 a and D2 b respectively synchronized with the timing clocks T2 a and T2 b.

The control signal generating part 903 detects the rises of the four demodulated timing clocks (timing clocks T1 a, T1 b, T2 a and T2 b) by using the control timing clock Tp having a cycle shorter than the shortest cycle of the timing clocks T1 and T2. The control signal generating part 903 sequentially outputs the data control signals for identifying the timing clocks of which rises are detected at the next cycle T[N+1] when the rises are detected within a control timing clock cycle T[N] and holds and outputs the data control signals when the rises are not detected.

In FIG. 10, since the timing clocks T1 a and T2 a rise at the cycle T[1], the data control signal sequentially outputs T1 a and T2 a at the cycle T[2]. Since the timing clocks T1 a and T2 b rise at the cycle T[3], the data control signal sequentially outputs T1 a and T2 b at the cycle T[4]. Since any timing clock does not have the rise at the cycle T[4], the data control signal holds the prior T2 b.

The multiplexing part 904 selects the demodulated data D1 a, D1 b, D2 a and D2 b by the data control signal to generate and output the multiplexed data. In FIG. 10, the data control signal having the cycle T[2] represents T1 a and T2 a, the contents AO and BO of D1 a and D2 a respectively corresponded are outputted as the multiplexed data.

The first clock generating part 905 detects the rises of the timing clocks T1 a and T2 b at the control timing clock cycle T, and generates and outputs the first multiplexed timing clock Ta having the rise during the output period of the data control signal within the next cycle T[N+1] when detecting the rise of any one within the control timing clock cycle T[N].

The second clock generating part 906 also detects the rises of the timing clocks T2 a and T2 b at the control timing clock cycle T[N] similarly to the first clock generating part 905, and generates and outputs the second multiplexed timing clock Tb at the next cycle T[N+1].

As described above, in embodiment 3, by using the control timing clock Tp higher-rate than the timing clocks T1 and T2 to extend the data without detecting the rates of the first and second demodulated data D1 and D2, since the two demodulated data D1 and D2 which operate asynchronously can be easily used with the multiplexed data synchronized with a single clock, the scale of the circuit and the number of the design processes can be reduced.

Moreover, the control timing clock cycle T is 1/m (m=counting numbers □ 2) of the timing clock T1 or T2, whereby the synchronous design can be performed, the improvement of the design efficiency can be further planned.

In addition, it is preferable that the data extending parts 901 and 902 holds the demodulated data at the rises or falls of the timing clocks T1 and T2.

Embodiment 4

Hereinafter, a receiving apparatus in embodiment 4 of the present invention will be described with reference to FIG. 11. Moreover, in FIG. 11, same reference numerals, and a and b for identifying two systems will be given to components same as those in FIG. 1, and the description thereof will be omitted.

The receiving apparatus in embodiment 4 of the present invention receiving 4n-type received signals (n=positive integer □ 1; different received signals A, B, C and D in four broad systems in FIG. 11) parallely disposes the receiving apparatus 100 indicated in embodiment 1 in 2n rows (2n rows in FIG. 11) and generates 4n-type timing clock and 2n-type multiplexed data to output the 4n-type timing clock and 2n-type multiplexed data to the A/V decoder 107. Moreover, the receiving apparatus the demodulation parts suitable for the broadcast systems of the respective received signals.

As described above, in embodiment 4, in case that the 4n-type received signal is received, 2n receiving apparatuses indicated in embodiment 1 are parallely disposed so as to output the 4n-type received signal as the 2n-type multiplexed data. In addition, the two demodulated data can be multiplexed without using a large-scale memory, the design can be easily performed and increment of the board dimension can be prevented so as to provide the receiving apparatus inexpensively.

Moreover, the receiving apparatus in embodiment 4 has the configuration of the receiving apparatus described in embodiment 1, but may have the configuration of the receiving apparatus in embodiment 2 or 3.

In addition, two demodulation parts are configured as the demodulation part, but the demodulation parts of the respective broadcast systems may be configured.

Further, the different received signals A, B, C and D of the four broadcast systems are adopted as the 4n-type received signal, but the received signals of all the same broadcast systems or of the broadcast system mixing a same broadcast system and a different broadcast system may be adopted as the 4n-type received signal.

Embodiment 5

Hereinafter, a receiving method in embodiment 5 of the present invention will be described with reference to FIGS. 12 and 13.

FIG. 12 is a block diagram of a processor which executes the receiving method of embodiment 5.

In FIG. 12, reference numerals 1201 and 1202 are an input I/F for inputting received signals A and B of the respective broadcast systems. Reference numeral 1203 is a general built-in memory. In addition, reference numeral 1204 is a CPU for performing the control and the operation, and reference numeral 1205 is a ROM for storing a control program. Further, reference numeral 1207 is an output I/F for outputting the demodulated data multiplexing the demodulated data demodulating the respective received signals and the timing clocks respectively synchronized with the demodulated to be multiplexed to the A/V decoder 107. A CPU 1204, a ROM 1205 and an output IF 1207 are connected to the input I/Fs 1201 and 1202 via the built-in memory 1203.

The receiving method by the CPU 1204 is described according to a flow cart of FIG. 13.

Step-S1 (Demodulating Step)

First of all, respective received signals A and B are demodulated, based on respective broadcast systems, and respective demodulated data D1 and D2 are generated in a byte so as to generate the timing clocks T1 and T2 synchronized therewith.

Step-S2 (Rate Determining Step)

Next, rates of the two timing clocks T1 and T2 generated in step S1 are determined, and the two timing clocks T1 and T2 are outputted as a high-rate timing clock TH and a low-rate timing clock TL. In addition, the two demodulated data D1 and D2 generated in step S1 are outputted as high-rate demodulated data DH and low-rate demodulated data DL synchronized with the high-rate timing clock TH and the low-rate timing clock TL.

Step-S3 (Clock Generating Step)

Next, a low-rate timing clock having an average frequency same as the low-rate timing clock TL is generated by being synchronized with high-rate timing clock TH.

More specifically, the clock generating step S3 is configured by steps S4 to S6 described below.

Step-S4 (Storing Step)

A counting value of the low-rate timing clock TL counted at every predetermined cycle n of the high-rate timing clock TH is stored as a control value M.

Step-S5 (Mask Signal Generation Processing Step)

Next, when the counting value of the high-rate timing clock TH is not larger than the control value M, a logical value “1” is outputted and the counting value is larger than the control value M, a logical value “0” is outputted.

Step-S6 (Mask Processing Step)

Next, when a mask signal outputted from step-S5 has a logical value “1”, the high-rate timing clock TH is outputted and the mask signal has a logical value “0”, a logical value “L” is outputted as the low-rate timing clock.

Step-S7 (Multiplex Processing Step)

Following the clock generating step S3 (S4 to S6), when the low-rate timing clock has a logical value “1”, the low-rate demodulated data DL are selected and outputted, and when the low-rate timing clock has a logical value “0”, the high-rate demodulated data DH are selected and outputted.

As described above, in embodiment 5, since the two demodulated data D1 and D2 can be multiplexed in a byte by means of the configuration of the general processor, the capacity of the general memory 1203 can be largely reduced, lowering a cost of the receiving apparatus can be realized and the timing clock outputted to the A/V decoder is synchronized with the high-rate timing clock, and the timing restriction of the connected A/V decoder 107 is relaxed, a cost of a whole system can be reduced by using an inexpensive components. In addition, eve though rates of the two demodulated data D1 and D2 outputted by the demodulation processing, and the two timing clocks T1 and T2 synchronized therewith are not known, the two demodulated data D1 and D2 can be multiplexed.

INDUSTRIAL APPLICABILITY

In a receiving apparatus of the present invention, two demodulated data can be multiplexed by adding a small-scale circuit without a large-scale memory, thus a cost reduction by the reduction of the circuit scale and low power consumption can be realized by the reduction of the circuit scale. A timing clock synchronized demodulated data to be multiplexed can be synchronized with high-rate timing clock or a signal timing clock such as a high-rate timing clock, timing restriction of a latter A/V decoder can be relaxed. Thus, a more inexpensive system can be constructed. Consequently, the receiving apparatus can be applied to a system which receives a plurality of broadcast systems at one site in a remote place and widely transmits the received data. 

1. A receiving apparatus for receiving two received signals of digital broadcasting of different broadcast systems or same broadcast systems, the receiving apparatus comprising: a first demodulation part and a second demodulation part that respectively input the two received signals, and output demodulated data thereof and timing clocks respectively synchronized with the demodulated data; a clock generating part that generates and outputs the respective timing clocks of the two demodulated data to be multiplexed, based on the two timing clock outputted from the first and second demodulation parts, and outputs control signals for multiplexing the two demodulated data; and a multiplexing part that multiplexes by a byte the demodulated data outputted from the first and second demodulation parts, based on the control signals outputted from the clock generating part.
 2. The receiving apparatus according to claim 1, further comprising: a first selection part that selects and outputs high-rate timing clocks and high-rate demodulated data synchronized therewith, and lower-rate timing clocks and demodulated data synchronized therewith, alternatively from two timing clocks and two demodulated data outputted from the first and second demodulation parts.
 3. The receiving apparatus according to claim 2, further comprising: a rate determination part that compares respective rates of the timing clocks outputted from the first and second demodulation parts, determines which clock is the higher-rate, and outputs the determining result to the first selection part by a control signal, wherein the first selection part selects high-rate timing clocks and high-rate demodulated data synchronized therewith, and low-rate timing clocks and low-rate demodulated data synchronized therewith.
 4. The receiving apparatus according to claim 3, wherein the rate determination part includes: a first clock counting unit and a second clock counting unit that count respective number of clocks of two timing clocks outputted from the first and second demodulation parts, and outputs initialization signals at a predetermined cycle, each being initialized by the outputting of any one of the initialization signals; and an identification unit that inputs the first and second initialization signals respectively outputted from the first and second clock counting units, and as a control signal to be outputted to the first selection part, outputs a first logical value when an output of the first initialization signal is inputted in advance or simultaneously and an inverting value of the first logical value when the second initialization value is inputted in advance.
 5. The receiving apparatus according to claim 2, wherein the clock generating part includes: an edge detecting unit that outputs the high-rate timing clock outputted from the first selection part as the high-rate timing clock, detects simultaneous rises of two high-rate timing clock and low-rate timing clock outputted from the first selection part, and outputs a second logical value when the rises are simultaneous and an inverting value of the second logical value when the rises are not simultaneous; a delaying unit that delays and outputs the low-rate timing clocks outputted from the first selection part; a second selection unit that inputs the low-rate timing clock outputted from the first selection part and the low-rate timing clock delayed by the delaying unit, selects the low-rate timing clock delayed by the delaying unit when the inputted low-rate timing clock has the second logical value and the low-rate timing clock outputted from the first selection part when the inputted low-rate timing clock has the inverting value of the second logical value, and outputs the inputted timing clock as the low-rate timing clock; and a control signal generating unit that inputs the high-rate timing clock and the low-rate timing clock outputted from the second selection unit, outputs a third logical value when the high-rate timing clock rises and an inverting value of the third logical value when the low-rate timing clock rises, as the control signal for multiplexing the two demodulated data to be outputted to the multiplexing part, and holds the value when the rise does not exist.
 6. A receiving apparatus for receiving two received signals of digital broadcasting of different broadcast systems or same broadcasting systems, the receiving apparatus comprising: a first demodulating part and a second demodulating part that respectively input the two received signals, and output demodulated data thereof and timing clocks respectively synchronized with the demodulated data; a clock generating part that outputs a high-rate timing clock out of timing clocks outputted from the first and second demodulation parts as the high-rate timing clock, and generates and outputs a clock having a same average frequency as a low-rate timing clock and synchronized with the high-rate timing clock as the low-rate timing clock; and a multiplexing part that multiplexes, by a byte, demodulated data outputted from the first and second demodulation parts, based on the low-rate timing clock outputted from the clock generating part.
 7. The receiving apparatus according to claim 6, further comprising: a first clock counting part and a second clock counting part that count respective number of clocks of two timing clocks outputted from the first and second demodulation parts to output counted number, and outputs initialization signals at a predetermined cycle, each being initialized by the outputting of any one of the initialization signals; an identification part that inputs the first and second initialization signals respectively outputted from the first and second clock counting units, and outputs a first logical value when an output of the first initialization signal is inputted in advance or simultaneously as a control signal to be inputted to the first selection part and an inverting value of the first logical value when the second initialization value is inputted in advance; and a first selection part that outputs the first timing clock as the high-rate timing clock and the first demodulated data as the high-rate demodulated data when the control signal has the first logical value, and outputs the second demodulated data as the high-rate demodulated data when the control signal has the inverting value of the first logical value, by using as the inputs a first timing clock and a first demodulated data outputted from the first demodulation part, and a second timing clock and a second demodulated data outputted from the second demodulation part, and a control signal outputted from the identification part.
 8. The receiving apparatus according to claim 7, wherein the clock generating part includes: a third selection unit that outputs a counting value of the first clock counting part when the control signal has the first logical value and outputs a counting value of the second clock counting part when the control signal has the inverting value of the first logical value, by using as the inputs respective counting values and initialization signals of the first and second clock counting parts and the control signal of the identification part; a storing unit that stores the counting value of the second clock counting value as a control value when the control signal has the first logical value, and stores and outputs the counting value of the first clock counting value as the control value when the control signal has the inverting value of the first logical value, when the initialization signals are inputted by using as the inputs the respective counting values and initialization values of the first and second clock counting parts and the control signals of the identification part; a mask signal generating unit that outputs a fourth logical value as a mask signal when the counting value of the third selection unit is not larger than the control value and outputs an inverting value of the fourth logical value as a mask signal when the counting value of the third selection unit is larger than the control value, by using the counting value outputted from the third selection unit as the inputs; a mask unit that outputs the high-rate timing clock when the mask signal has the fourth logical value and outputs a logical value “L” as the low-rate timing clock when the mask signal has the inverting value of the fourth logical value, by using as the inputs the mask signal outputted from the mask signal generating unit and the high-rate timing clock outputted from the first selection part; and a logic inverting circuit that logic-inverts the high-rate timing clock outputted from the first selection part, and outputs the logic-inverted clock as the high-rate timing clock.
 9. A receiving apparatus for receiving two received signal of digital broadcasting of different broadcast systems or same broadcast systems, the receiving apparatus comprising: a first demodulation part and a second demodulation part that respectively input the two received signals, and output demodulated data thereof and timing clocks respectively synchronized with the demodulated data; a first data extension part that inputs the demodulated data from the first demodulation part and the timing clocks synchronized therewith, and outputs two systems including odd-time timing clocks and odd-time demodulated data synchronized therewith, and even-time timing clocks and even-time demodulated data synchronized therewith; a second data extension part that inputs the demodulated data from the second demodulation part and the timing clocks synchronized therewith, and outputs two systems including odd-time timing clocks and odd-time demodulated data synchronized therewith, and even-time timing clocks and even-time demodulated data synchronized therewith; a control signal generating part that inputs a control timing clock having cycles not larger than cycles of short one of the two timing clocks outputted from the first and second demodulation parts, and four demodulated timing clocks outputted from the first and second data extension parts, and detects the demodulated timing clocks having a rise within the control timing clock cycle so as to output an identification control signal in a next cycle; a multiplexing part that selects, based on the identification control signal outputted from the control signal generating part, the demodulated data synchronized with the identification control signal and outputted from the first and second data extension parts; a first clock generating part that inputs the control timing clock and the timing clock outputted from the first data extension part, and detects the rise within the control timing clock cycle to generate a first multiplexed timing clock having the rise within the identification control signal period of the next cycle; and a second clock generating part that inputs the control timing clock and the timing clock outputted from the second data extension part, and detects the rise within the control timing clock cycle to generate a second multiplexed timing clock having the rise within the identification control signal of the next cycle.
 10. A receiving apparatus comprising 2n (n=positive integer≧1) units of receiving apparatuses according to claim 1 arranged in parallel, wherein the receiving apparatus inputs 4n-type received signal, and generates and outputs 4n-type timing clocks and 2n-type multiplexed data.
 11. A receiving apparatus comprising: the receiving apparatus according to claim 1; and a video signal processing device that inputs multiplexed data of two demodulated data outputted from the receiving apparatus and respective timing clocks of the multiplexed two demodulated data, and uses any one or both of the two demodulated data out of the multiplexed data as received data.
 12. A method of receiving two received signals of digital broadcasting of different broadcast systems or same broadcast systems, the method comprising: demodulating the two received signals based on the respective systems, generating respective demodulated data by a byte, and generating timing clocks synchronized therewith; determining rates of two generated timing clocks, outputting two timing clocks as a high-rate timing clock and a low-rate timing clock, and outputting the two generated demodulated data as high-rate demodulated data and low-rate demodulated data synchronized with the high-rate timing clock and the low-rate timing clock, respectively; storing a counting value of the low-rate timing clock counted at every predetermined cycle of the high-rate timing clock as a control value; outputting a logical value “1” when the counting value of the high-rate timing clock is not larger than the stored control value and a logical value “0” when the counting value is lager than the control value, as a mask signal; outputting the high-rate timing clock when the mask signal has a logical value “1”, and the logical value “L” as the low-rate timing clock when the low-rate timing clock has a logical value “0”; and selecting and outputting the low-rate demodulated data when the low-rate timing clock has a logical value “1”, and the high-rate demodulated data when the low-rate timing clock has a logical value “0”. 